Analysis of the NAND Flash device garbage collection algorithms under lack of memory conditions

A number of existing packages of applied programs for computer modeling of electron-optical systems of sources of charged particles built on the basis of analytical synthesis models and numerical methods of analysis are considered. The analysis of the main advantages and disadvantages of the packages MAGIC, MAFIA, CEM, KARAT, POISSON, TAU, ERA, BEAMCAD and their functionality is carried out

Analysis of the NAND Flash device garbage collection algorithms under lack of memory conditions

A number of existing packages of applied programs for computer modeling of electron-optical systems of sources of charged particles built on the basis of analytical synthesis models and numerical methods of analysis are considered. The analysis of the main advantages and disadvantages of the packages MAGIC, MAFIA, CEM, KARAT, POISSON, TAU, ERA, BEAMCAD and their functionality is carried out

FPGA Based Arbiter Physical Unclonable Function Implementation with Reduced Hardware Overhead

The paper presents a new architecture of symmetric paths of the arbiter PUF, providing efficient use of the hardware resources of LUT blocks for various Xilinx Artix-7 FPGA family

NAND Flash Memory Devices Security Enhancement Based on Physical Unclonable Functions

True random number generators (TRNGs) are used in a wide range of applications (e.g., cryptography, statistical sampling, simulation, computer games, etc.). TRNG can be implemented as a part of NAND flash memory device controller and used to support Trusted Computing Group (TCG) standard. The main advantage of TRNGs comparing to pseudorandom number generators (PRNG) is the uniqueness and unpredictability of their produced output values. TRNG is a device or a part of a device that generates random numbers based on some intrinsic physical process. One of the possible ways of extracting random data from electronic devices is to implement physical unclonable functions (PUFs)

ОБЗОР МЕТОДОВ АКТИВНОЙ ИДЕНТИФИКАЦИИ ЦИФРОВЫХ УСТРОЙСТВ

The paper presents existing active hardware metering approaches. The motivation of using active metering approaches by fabless integrated circuits design companies is given. The finite state machine based and asymmetrical cryptography based methods are presented. The advantages and disadvantages of existing active metering approaches are analyzed. The potential solution for modern technique issues are proposed.Рассматриваются существующие методы активной идентификации цифровых устройств и приводится обоснование необходимости использования таких методов компаниями – проектировщиками интегральных схем. Представляется описание методов, основанных на модифицирующих преобразованиях цифрового конечного автомата и протоколах асимметричного шифрования. Анализируются преимущества и недостатки методов активной идентификации и предлагаются пути решения проблем, актуальных в настоящее время

ФИЗИЧЕСКАЯ КРИПТОГРАФИЯ И ЗАЩИТА ЦИФРОВЫХ УСТРОЙСТВ

The article presents the main scientific results and practical achievements obtained by undergraduate and graduate students of Computer Science department of BSUIR under the supervision of professor A.A. Ivaniuk during the period from 2014 to 2018. The original circuit solutions in the field of synthesis of digital physically unclonable functions are presented. The area of physically unclonable functions was first time published in the journal «Informatics» by professor of Software for information technologies department of BSUIR, doctor of technical sciences V.N. Yarmolik, which is a famous domestic scientist in area of reliable digital devices and systems design. New methods and algorithms for unclonable identification and authentication of digital devices are described. The paper also presents the results obtained in the field of random number sequences generation. In addition, the results on the methods of hardware watermarks injection and functional obfuscation of digital devices are given.В статье представлены основные научные результаты и достижения, полученные аспирантами, магистрантами и соискателями кафедры информатики БГУИР под научным руководством профессора А.А. Иванюка в период с 2014 по 2018 год. Приведены оригинальные схемотехнические решения в области синтеза цифровых физически неклонируемых функций. Впервые проблематика физически неклонируемых функций была опубликована в 2011 году в журнале «Информатика» профессором кафедры ПОИТ БГУИР д.т.н., профессором В.Н. Ярмоликом, являющимся известным отечественным ученым в области проектирования надежных цифровых устройств и систем. В данной статье приведены новые методы и алгоритмы неклонируемой идентификации и аутентификации цифровых устройств. Представлены результаты, полученные в области генерирования случайных числовых последовательностей. Кроме того, приведены результаты по методам реализации аппаратных водяных знаков и функциональной обфускации цифровых устройств

МЕТОД УВЕЛИЧЕНИЯ СТАБИЛЬНОСТИ ФИЗИЧЕСКИ НЕКЛОНИРУЕМОЙ ФУНКЦИИ ТИПА «АРБИТР»

The paper presents a reliability enhancement method for an arbiter physically unclonable function (A-PUF). The proposed technique has reasonable challenge-response generation time and does not cause additional hardware overheads. A time difference of a test pulse delay has been used as a basis for A-PUF parametric model development. The proposed approach has been verified on a real programmable logic device.Предлагается метод повышения стабильности физически неклонируемой функции типа «арбитр» без увеличения затрат на аппаратное обеспечение и значительного роста времени получения ответа. Предлагается развернутая параметрическая модель формирования временной разницы тестового сигнала на входах арбитра. Проводится проверка метода на реальных устройствах программируемой логики

Arbiter PUF based FPGA chip identification and authentication methods with enhanced reliability and modeling attack resistance

The last 25 years have witnessed an exponential growth of the number of devices connected to the Internet of Things (IoT) from a million in 1992 to 20 billions in 2017. Despite IoT has become widespread, this concept is still not well-established due to several reasons such as lack of standards, security and data protection issues, maintenance cost, etc. Since much of the sensitive personal data is transmitted via IoT devices, secure access control to this data can be highlighted as one of the most important challenges for this area. Classical hardware cryptographic methods have two major disadvantages, signifi cant hardware overhead required for its implementation and non-volatile memory for secret key storage. One effective way to provide secure chip authentication with low overhead is the Physical Unclonable Functions (PUF). They are widely used as a cryptographic primitive to avoid the need for storing the key or secret that can be used to retrieve the device key in the non-volatile memory. PUF uses the intrinsic integrated circuit's manufacturing process variations to generate unique and random response to a given challenge to identify a chip. For reliable key generation, it is required that the responses of the PUF are highly stable against operating environment variations such as temperature and supply voltage variations. One of the most well-explored PUF design is Arbiter PUF (A-PUF), which has been utilized by Verayo to implement RFID ICs as well as by Xilinx to include PUF IP as a hardware root of trust for its new Zynq UltraScale+ devices. However, porting of existing Arbiter PUF designs that are not implemented as ASIC cores into FPGA platform suffers from poor reliability due to routing constraints. On the other hand, improving temporal stability of A-PUF responses makes the circuit vulnerable to modeling attack using machine learning methods. Thus, this research targets design and implementation of reliable and secure A-PUF on FPGA chips without built-in PUF. It also aims to overcome the limitation of using existing PUF IPs for authentication of FPGA-based IoT devices. This thesis presents a comprehensive overview of state-of-the-art PUF designs and their ASIC and FPGA implementations. As a means for reliability enhancement, a new hybrid PUF based on A-PUF is proposed. Using the SR latch instead of D Flip-Flop as an arbiter makes it possible to expand the original response states to a ternary set stable 0, stable 1 and High Frequency Oscillation (HFO). The enhanced reliability and uniqueness were attested by experimental results implemented on FPGA platform. To further improve its reliability to the ideal 1.0 over a wide range (from -45 C to +90 C) of temperature, a challenge classi cation algorithm is introduced. The proposed method has been tested on identical FPGA chips of two different families and has shown no degradation on uniqueness. To prevent modeling attack, two approaches based on non-linear challenge processing are presented in this thesis. It has been shown that the proposed techniques are resilient against modeling attack by different machine learning algorithms, including the most advanced Covariance Matrix Adaptation Evolutionary Strategy (CMA-ES). The abovementioned contributions are utilized to build a low-cost authentication protocol based on a highly accurate model of A-PUF.Doctor of Philosoph